The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a semiconductor memory device in which side surfaces of neighboring bit lines do not face each other to reduce a capacitance of a parasitic capacitor formed between the neighboring bit lines for enabling an operation speed of semiconductor memory device to be improved and to prevent a void from being generated in a contact plug.
In recent years, research on a semiconductor memory device with high integration and improved performance has been actively conducted. A problem caused by a high integration NAND flash memory device is described in detail below.
The NAND-type flash memory device consists of a plurality of cell strings. Each cell string comprises a source select transistor, a plurality memory cells and a drain select transistor which are connected to each other in series. A source of the source select transistor is connected to a common source line, and a drain of the drain select transistor is connected to a bit line. Gates of the source select transistors are connected to each other to form a source select line, gates of the drain select transistors are connected to each other to form a drain select line, and gates of the memory cells are connected to each other to form a word line.
The gate pattern including the word line, the source select line and the drain select line has a structure in which a tunnel insulating layer, a floating gate, a dielectric layer and a control gate are sequentially laminated. The dielectric layer comprises contact holes through which the floating gate of the source select line and the floating gate of the drain select line are exposed. The floating gate exposed through the contact holes is electrically connected to the control gate.
A lower structure of the flash memory device including the gate pattern is covered with an insulating layer to isolate the lower structure from an upper structure including the common source line and the bit line. The upper structure and the lower structure are electrically connected through a contact hole formed in the insulating layer and a contact plug formed in the contact hole.
As memory devices become highly integrated, a distance between the bit lines becomes smaller. An insulating layer is formed between the bit lines and side surfaces of the bit lines face each other. Thus, a capacitance of a parasitic capacitor formed between the bit lines is increased in inverse-proportion to the distance between the bit lines. An increase of the capacitance of the parasitic capacitor formed between the bit lines causes a resistive capacitive (RC) properties to decrease an operation speed of the semiconductor memory device.
Accordingly, a high integration semiconductor memory device having a reduced capacitance of a parasitic capacitor formed between the bit lines is required.
As semiconductor memory devices become more highly integrated, a plurality of patterns are formed with a stack structure in which an insulating layer is disposed between the patterns. Accordingly, an aspect ratio of the contact hole is increased. An increase of the aspect ratio of the contact hole causes generation of a void when a contact plug is formed, and the void results in a poor quality semiconductor memory device.
Accordingly, a semiconductor memory device is required which is suitable for high integration and is capable of preventing a void from being generated in a contact plug.